Shallow trench isolation (STI) is gaining acceptance as the dominant transistor isolation process for the submicron generation. One of the drawbacks of STI is the sharp corners at the isolation edge where the silicon substrate and oxide intercept. One option is to minimize the exposure of silicon corners. Exposed silicon corners will upset the electrical characteristics of a transistor device. U.S. Pat. No. 5,433,794, incorporated by reference herein, discusses one method for protecting silicon corners in an STI process.